Research And Design Of 6 Bit High Speed CMOS Digital To Analog Converter Integrated Circuit

As an interface from data system to analog system, digital to analog converter (DAC) becomes more and more important. Rapid development of wireless communication technology improves the need of high speed DAC. And the performance of DAC has become the bottleneck of the communication system. So it’s valuable to study and design a high speed DAC.This paper introduces the principle of DAC and some key index. Then analyzes the properties and implementations of three kinds of DAC:resistance type DAC、capacitive type DAC and current steering DAC. Current steering DAC is widely used in high speed field because of its intrinsic high speed, it puts the current to load directly and there is no need to use buffer. Based on this, this paper discusses the key factors which affect static and dynamic performance of the current steering DAC. Detailed analyzes about the random error and systematic error of current source array, relationship between current source output impedance and performance of current steering DAC have been shown. Other parts of current steering DAC have been analyzed too, including band-gap reference voltage, bias of cascade current source, input register, decoder, latch, switch control signal and so on.The 6-bit DAC have been desiged based on 65nm CMOS technology, which consists of 4MSBs and 2LSBs, trading off between the precision and complexity of circuit. The DAC concludes analog part and digital part. The analog part provides accurate current source array. Inside current sources help improve stability and integration level of the circuit. Digital part converts the input signals into the signals which used to control the differential switchs, and synchronize the control signals. The 8-GSample/s conversion rate has been obtained by fully custom designed thermometer decoder and synchronization circuit. It is important to make sure the current source never close during the switch operation, a modulater has been added to converte the differential control signal to signals which have a high intersection.This thesis have finished schematic design, layout design and system simulation The 6 bit DAC exhibits good static performance thanks to the big size of current source and the common-centroid scheme. It’s SFDR better than 42 dB from DC to Nyquist frequency with a 5GHz sampling frequency. When sampling frequency up to 8GHz, SFDR better than 34 dB until output frequency up to 2.7 GHz. The full scale output Current of the DAC is 2.52 mA and the power consumption is 15.7 mW at 8GHz Sampling. The DAC is implemented in TSMC 65 nm low power CMOS technology and occupies 0.33 mm2 with pad and the chip has been manufactured.