Advanced Study On Design Of CMOS Current-steering DACs

The recent growth of applications using wide-band data transmission such as telecommunication and digital video systems requires high-speed high-resolution data converters (A/D and D/A) and System On Chip (SOC) with high performance data converters as part of building blocks. CMOS current steering DACs are inherently fast, silicon area and power effective, easy to integrate in standard digital CMOS technologies and therefore the architecture of choice for such applications.As a new try of SOC study and design methods, we have built high abstraction level models for CMOS current steering DACs, to simulate and predict the performance of DAC with math tool Matlab and advanced hardware description language Verilog-AMS. In this paper, first the models of several analog units and typical mixed signal systems are studied and simulated, then the affects of matching errors of current source to performance of DAC and the affects of output resistance of current source to performance of DAC are described emphatically. With corresponding models how the matching errors and output resistance of current source affect the NL, SNDR and SFDR of DAC is analyzed and simulated in detail.At last, as a practical design example, a 5V, 14-bit high speed segmented current-steering DAC based on the TSMC 0.35μm mixed-signal CMOS technology for telecommunication applications is also described.