Research And Design Of 8-bit High Speed DAC

With the rapid development of modern communication technology,computer technology and integrated circuit manufacturing technology,the emergence of new technologies,led by 5G and the Internet of Things,has a higher requirement on the speed of information processing.Digital-Analog Converter(DAC)is an important device to convert digital quantity into analog quantity.Its performance has become one of the bottlenecks that restrict the speed of information transmission in communication system.Therefore,the research and design of high-speed DAC is of great significance.In this thesis,architectures of DAC are firstly discussed.Then current steering DAC which is suitable for high-speed DAC design is selected.Various factors and parameters that affect the static and dynamic performance of DAC are discussed,including mismatch of current source and selection of decoding method.The affecting parameters mainly include high-frequency output impedance of current source.According to the analysis,the minimum size of current source is calculated.Then the circuit design and simulation of each key module of DAC are carried out.At last,the layout design of the high-speed DAC is introduced,and the test scheme is given.Based on the 40 nm LP CMOS process,this thesis designs an 8-bit high speed current steering DAC with the highest sampling rate up to 10 Gsps.It adopts "4+4" segmentation decoding and thermometer codes are used for both high and low decoding.The whole circuit contains analog part and digital part.The analog part provides stable bias voltage for the current source array.Analog part includes bandgap reference voltage source,voltage to current circuit,bias voltage generation circuit and current source array.The bandgap voltage reference adopts a structure suitable for low supply voltage to generate a temperature independent voltage reference.The digital part contains decoding circuit,switch array,input register,switch driving circuit and clock driving circuit.The input register adopts level trigger mode to ensure the signal synchronization.The switch driving circuit generates a pair of differential driving signals to drive and control the switch.The output is obtained by superposition of different weight current on the load resistance.This design uses 1.1V power supply voltage.The analog part and the digital part are supplied separately with a total power consumption of the circuit being about 16.48 mw.The area of chip is 600 um *625um.DNL is less than 0.3lsb and the INL is less than 0.5lsb.When the clock frequency is 10 GHz,the SFDR of the output signal reaches 44.49 db in the whole sampling range.