A 16-bit High-Speed Segmented Current-Steering CMOS D/A Converter Design

High-speed, high-resolution CMOS D/A converter, being the most important part of software radio SOC chip IP core is a key component of modern mobile communications, broadband imaging radar systems and modern wireless networks. It makes a very important positon and role on the domain above. The speed and the resolution of the D/A converter are the most important parameters to determine the performance of mobile communications and software radio systems. High-speed(more than 500MHz) and high-resolution(more than 12 bit) D/A converter is urgent needed in the domain above. It is the forefront and key difficulty of VLSI technology, is the restriction to the development of the domain above. The research and exploiture on high-speed and high-resolution D/A converter chip is urgent needed for the development of mobile communications, radar and wireless networks system.Based on SMIC 0.18μm 1P6M standard CMOS process, a 16 bit high-speed segmented current-steering D/A converter is design in this thesis. The sampling clock frequency is 1G Hz, the segmented structure is 6+5+5, while the 6 most significant bits and the 5 intermediate significant bits are thermometer decode, and the 5 least significant bits are binary-weighted decode. Reference current and cascode structure are used to get a precise and high-output resistance current source. A low swing and low cross current switch drive schematic is design to reduses the glitch. Providing metal fuse current source calibration schematic makes sure the current unit matching. Using duplicate supply, while digital supply is 1.8V and analog supply is 3.3V. This thesis use a differential output structure, full-scale output current is 10mA, and we can transfer it to output voltage with a 50? resister.Based on Cadence environment, using Spectre to make a simulation to the D/A converter design in this thesis, and the simulation results are that, a settling time of 1.4ns; INL about±1.1LSB, DNL of±0.6LSB; when the input signal is a sinusoid with 1M Hz, and the sampling clock frequency is 1G Hz, the SFDR is 78.1dB; the whole power consumption is 123.39mW; the core chip area is about 1.6mm×1.4mm, it can be used in modern mobile communications and software radio system.