Research And Realization Of A 12bit Low Power SAR ADC

As the bridge between analog circuit and DSP, analog-to-digital converters(ADC) are usually used in the filed such as radar, image sensor and touch screen of mobile phone, and so on. Among the common structure of ADCs, the successive approximation register(SAR) analog-to-digital converters are extensively used in low power consumption and small area applications for its principle relatively simple. Benefit from the advancement of CMOS technology such as the small feature size, the superiority of SAR architecture is getting more obvious, and SAR ADC is becoming a hot research topic.To satisfy the high-resolution and low-power requirements of Power Line Carrier(PLC) system, a 12 bit 4MS/s SAR ADC is researched and realized. In addition, a switching scheme is proposed for charge redistribution SAR ADC. The ADC uses an asynchronous control logic to avoid the using of high frequency clock, and a dynamic comparator is used to minimize power. Bootstrapped switch is used to improve linearity, and an integrated voltage reference and buffer are employed. The various nonlinear factors such as capacitor mismatch are analyzed and modeled by using MATLAB. Meanwhile, with the help of multiple voltage references, an energy- and area-efficient switching procedure is presented.The ADC with the proposed switching procedure can save 99.4% switching energy and achieve a 8× reduction in total capacitance compared to the conventional SAR ADC. After layout parasitic extraction, the proposed ADC has been post-simulated in 0.18 ?m CMOS technology. At a 1.8-V supply and 1.57MS/s, the ADC achieves a SNDR of 70.2dB, SFDR and ENOB is 80.62 dB and 11.36 bits respectively, while dissipating 0.9mW resulting in a figure-of-merit(FOM) of 109fJ/conversion-step. The test results show that the proposed ADC can work properly and satisfy the requirements of system.