Design Of An Ultra Low Power SAR ADC For Implantable Medical Devices

With the development of information technology and the enhancement of civic health awareness, the research of implantable medical devices has become a hotspot. As a key module of the system, analog-to-digital converter(ADC) should have high resolution and low power. Among various ADC architectures, successive approximation register(SAR) ADC is a better choice to achieve this goal for sake of its simple structure and high energy efficiency. In this thesis, a 12 bits 10kS/s ultra low power SAR ADC with 0.6V power supply based on 55 nm CMOS process was proposed.Firstly, in order to reduce the power consumption of the comparator, this thesis analyzed the variation of the voltage difference between DAC outputs in the process of successive approximation of traditional vcm-based SAR ADC. And a voltage window principle was proposed, aiming at using different accuracy comparators to compare the voltage difference between DAC outputs. And on this basis, an ultra low power SAR ADC architecture was proposed with the use of the voltage window technology.Secondly, system modeling and simulation has been done for the proposed ultra low power SAR ADC with Matlab, and correctness of the structure has been verified. In order to achieve an optimum system performance, this thesis analyzed some non-ideal factors of the ultra low power SAR ADC which have impact on system performance. Including the capacitor mismatch and noise of the charge redistribution type DAC, the equivalent input offset voltage and input noise of the preamplifier and the latch, the size of the voltage window. And then added these non-ideal factors to the system model of the ADC to determine the tolerance range of each non-ideal factor, as a reference to direct the circuit design of each module.Thirdly, ultra low power design method has been used for each module. The power supply voltage was decreased to 0.6V. And stack forcing and multi-Vt design approaches are used to reduce the power consumption of the digital circuit. However, the low power supply voltage will decrease the linearity of the sampling switches. In this thesis, clock boosting technique was used to rise the gate voltage of the switches to improve the linearity of the sampling switches.Finally, the ultra low power SAR ADC was pre-simulated with Hspice. The pre-simulation results indicated that with a sampling frequency of 10 k S/s, the ADC achieved an SFDR of 83.9dB, an SNDR of 73.2dB, an ENOB of 11.87 bits. The total power consumption is 287.3nW, resulting in a FoM of 7.68fJ/Conv. The voltage window technique has effectively reduced 76.2% of the power consumption of the comparator, resulting in a 50.34% reduction of the total power consumption. Besides, the layout of the ultra low power SAR ADC was accomplished and post-simulated on 55 nm CMOS process. And the post-simulation results show that the SFDR is 77.8dB, the SNDR is 69.3dB and the ENOB is 11.22 bits. The power consumption is 624 nW, resulting in a Fo M of 26.17fJ/Conv. And the area of core layout is 435×210μm2.