Design And Model Of The Folding And Interpolating Analog-to-Digital Converter

High-speed ADC has a broad application and research prospect in the field of high-speed signal processing such as wireless communications and radar satellites. The parallel Flash ADC is the fastest one in all kinds of ADC. The system size grows exponentially as precision increasing. Folding and interpolating ADC uses folding and interpolating circuit to make sure fine and coarse quantification simultaneous which reduces system size and ensures high speed of original structure. Therefore it has a high practical value in the field of high-speed ADC, and becomes a hotspot.Firstly, this dissertation studies and analyzes the work process and implementation method of the system based on the principle of this ADC. According to the requirements of accuracy, speed and circuit size, we choose differential pairs folding and voltage interpolating architecture, and implement 8 bit system which is consist of 3 bit coarse and 5 bit fine structure. Secondly, according to the system-level model, we validate the work process and feasibility of ADC’s structure. Besides we analyze each module and non-ideal factors of the system which can aid circuit design. Finally, we design some key circuits of ADC. Differential pair preamplifiers are designed to reduce the effect of comparator input offset, and to complete coarse quantization with dynamic latched comparator. Differential pair folding circuit can produce the better linearity folding signals and suppress common-mode interference. The resistance structure of voltage interpolating circuit can improve the linearity by increasing the number of folding signals. The bit synchronization circuit ensures the fine and coarse signals synchronize to reduce the code error.This dissertation complete the circuit design and simulation based on TSMC 0.18um CMOS process,1.8V power supply voltage using the Spectre of Cadence. The result shows that, the ENOB can be 7.85bit with the sampling frequency of 250MHz and input signals of 121.09MHz. When the sampling frequency is 500MHz and the frequency of input signals is 101.56MHz, ENOB is 7.53bit.