Design Of Analog To Digital Converter Applied In Digitally Controlled DC-DC Converter

Recently the digitally controlled DC-DC converter is more and more used in electronic devices such as mobile phone, tablet and music player. Compared with analog controller, its parameters like switching frequency, voltage reference and accuracy is programmable. Thus the reliability of electronic devices can be improved, size can be reduced and operating time of battery can be saved. And in the structure of digital DC-DC controller, analog digital converter plays a key role. ADC has been used by digital controller to replace the error amplifier which belongs to analog controller and the cost of ADC is key to the total cost of digital controller. How to reduce the power consumption and area of ADC while maintaining the required static and dynamic performance has become a very important issue.This essay first introduces the working principle of digital DC-DC controller and the recent research works. Through the comparison with analog controller, the advantage of digital controller is introduced. Then this essay introduces the working principle of ADC and several typical architectures of ADC. Also the key performance indexes of ADC are presented. After showing several types of applications of ADC in digital DC-DC controller, this essay presents the requirements for ADC when used in digital controller.Based on the requirement, a new architecture is introduced, which use DPWM to share DLL with ADC, in which way, the power consumption and area of total system is saved. Based on the working principle, structure of ADC, DPWM and DLL, we present the challenges of this new technique.Using this new technique, we design a pulse modulated ADC. It converts the analog voltage to digital codes in two step:voltage to time; time to digital. And during the time to digital conversion, the DLL is used. The circuit design mainly includes ramp generator, comparator and time to digital converter. In the design of ramp generator, current stamp technique is combined with ramp generator to increase the linearity of the ramp signal without causing large power consumption. The comparator adopts the rail to rail structure to guarantee fixed offset in large input range. The time to digital converter uses the hybrid structure:counter for coarse quantification and delay line for fine quantification. Finally, through the logic optimization, the synchronization and match between coarse and fine quantification are guaranteed.Finally, this work is implemented under SMIC 0.13μm CMOS technology and PCB board is designed to measure the chip. The total area of this chip is only 0.03 mm2 and the power consumption is only 60μW. INL is-0.5 LSB～1.5 LSB, and DNL is-1 LSB～0.5 LSB. SINAD is 42.1dB and the ENOB is 6.7 bit. The measurement result shows that this chip meets the requirement of digital controller while keeping low power consumption and small area. Moreover, the technique of shared DLL between DPWM and ADC is verified.