Research And Realization Of Calibration Technique In Folding & Interpolating Analog-to-Digital Converter

In the digital oscilloscope, software radio technology, radar system and other applications, the operating frequency of electronic system has reached the level of GHz. As the core module of electronic system, the speed and precision of ADC has become a bottleneck of the performance improvement.Among the various implementation architectures of ADC, folding and interpolating structure shows its great potential in the filed of the ultra high speed and high precision. However, the accuracy of index is seriously affected by process variations beacuse of many open loop modules. It is necessary to introduce calibration technique to detect and compensate errors and nonlinear factors to ensure the realization of the high accuracy performance.This will be the core issue of this paper.Firstly, this paper investigates the current research situation of folding & interpolating ADC, and makes clear the potential of the folding and interpolating structure and the necessity of calibration technique in the high performance implementation, then a two channel time interleaved cascade architecture is adopted according to the index requirements. Secondly, based on the proposed architecture, this paper analysises the existing various error factors and studies various calibration technologies and signal integrity problems.This is good for the design of the ADC calibration scheme and calibration circuits.Finally, according to the channel offset mismatch error, the current steering DAC calibration circuit and the corresponding self-calibration based on foreground are designed to eliminate the effect of zero offset caused by process variation on the accuracy of the ADC; according to the sampling time mismatch error, the calibration problem is turned into the duty ratio detection skillfully, and the self calibration circuit based on the continuous time integrator is designed to reduce the influence on the dynamic performance of the ADC; according to the input signal integrity problem, impedance matching resistor is builted in the chip and impedance triming circuit is designed to ensure its accuracy.In this paper, calibration circuits of 10-bit 2GSPS ADC are designed based on the TSMC 0.18um CMOS process, and the circuit design and simulation are carried out by using the Spectre software of Cadence. Simulation results show that the calibration step of the current steering DAC calibration circuit is less than 1LSB, and resolution can reach up to 7 bit to calibrate the offset mismatch in dual channel analog path; the clock mismatch circuit can make the sampling clock error reduce from 100ps to 0.1ps within 2us when the clock frequency is 2GHz; input impedance triming circuit makes the differencial input impedance stable at 100Ω±1.7%,and meet the design requirements.