Research And Design Of Low Jitter Clock Duty Cycle Calibration Circuit

In the circuits such like Double Data Rate Synchronous Dynamic Radom Access Memory (DDR SDRAM), Pipeline ADC and Clock Data Recovery (CDR), a50%duty cycle clock could enhance the efficiency of the clock level in the greatest degree, thus ensures the correct function and good performance of a system. While with the clock frequency going faster, it is more and more vulnerable to PVT and noise for clock to generate duty-cycle offset. Clock duty cycle correction circuits are designed to solve this kind of problem.At first, this thesis introduces some non-ideal effects in Pipeline ADCs and then analyzes how the non-ideal effects of clock affect the Pipeline ADC’s performance. And then, it presents some typical structures of the clock duty cycle correction circuits. Digital, Analog and Hybrid structures are analyzed and compared. This thesis adopted a correction structure by further analysis of the basic unit circuits in the duty cycle correction circuit. As it is used for the high performance, high speed Pipeline ADCs, so the jitter performance of the duty cycle correction circuit is quite important. Thus the jitter of inverter and clock driver is also discussed in theory in the thesis. Finally, the low jitter clock duty cycle correction circuit is achieved in TSMC0.18um process.This design adopted the structure which uses a continuous-time integrator as its duty cycle detector and an current-starved inverter as its adjustor. It is achieved also with a clock driver and an indicate circuit. The results of spectre simulation shows: the adjustable duty cycle range is larger than10%～90%under50MHz clock input and it is roughly20%～80%under400MHz clock input; the additional jitter under200MHz clock input is lower than70fs and its correction error is lower than0.5%over its entire operating frequency range.