Design Of Low-Jitter Clock Duty Cycle Stabilizer For High-Speed A/D Converter

Low jitter clock signals are of great importance on improving high-speed ADCs'performance. Clock jitter caused by various factors usually leads to sampling dots shift, decrease of the ADCs'resolution and SNR, increase of output spectrum spur as well as bit error rate. So a duty cycle stabilizer (DCS) circuit which can provide low jitter sampling clock signals for ADCs is necessary.Under the summarization of the international and national research dynamic state on the duty cycle stabilizer circuit, the PLL technology is deeply studied, and the architecture of a low jitter DCS circuit is proposed in this thesis. Based on ASMC 0.35μm 3.3V BiCMOS mixed-signal process, relevant circuit blocks are designed, and much emphasis are placed on the study of the operational amplifier's performance influencing on clock jitter. After the circuit design, very consideration that needs to be taken in layout design is analyzed detailedly and the issues that need to be paid attention in the process of routing in some modules are significantly discussed, then the overall layout of the circuit is presented, which has a total area of 900μm×780μm.Simulation results under Cadence Spectre show that the DCS circuit can generate double groups of non-overlap clock signals. For the input clock at 125M, duty cycle ranged from 10% to 90% can be adjusted to 50%, and the average duty cycle error is less than 5%.The locking time of the loop is less than 2μs, and the peak-to-peak jitter is less than 12ps. The circuits can be applied for a14bit-125MSPS pipeline ADC.