Design And Implementation Of Clock Generator In High Speed ADC

In high-speed ADC, the high-precision clock is the guarantee of the entire chip. in order to solve the proplems such as noise, delay, single frequency and so on, we have to embed a high-precision clock generator into the high-speed ADC to meet the timing requirements of the high-speed ADC. Nowadays, the clock generator based on PLL is such a proposal that can provide a variety of frequencies with lower cost and more efficient. It also can meet the requirements of the important parameters of delay and jitter. But with the increasing of clock frequency, the design of PLL is becoming more and more difficulty, and the consumption of power is particularly prominent, especially in high frequency. Therefore, It is practical to propose a new design of clock generator. To the question, the delay, power, area and other important factors are considered and a clock generator that is suitable for 500M Hz pipleline ADC is designed.The design is achieved by TSMC 0.18 m mprocess. It is based on the delay-locked loop and redesigned to reduce the difficulty and power. The design consists of three modules: the clock buffer circuit, the duty-cycle correction circuit and frequency divider circuit. The clock buffer circuit is realized by the bicmos structure, it can efficiently zoom in the signal of clock and increase the driver ability of the signal. The duty-cycle correction circuit is based on the DLL circuit.It can be mainly divided into frequency synthesizer, charge pump detection circuit, delay circuit and shaper. It is used to adjust the duty-cycle of the clock to meet the precision requirements of ADC. The frequency divider circuit mainly completes the function of dividing frequence. A stable 50% duty -cycle clock is produced after the external clock is processed by the clock generator, and then it works as the control signals in the sample and holding circuit or the synchronization signals of other modules.