High-speed High-resolution Pipelined ADC Design And Research

Analog-to-digital converter is widely used in wireless communication. Considering the development trend, the society’s need of ADC has more requirements on resolution and speed. Applications of high-resolution high-speed ADCs become more and more important that wireless base station, radar as well as medical imaging all need this kind of ADCs. Moreover, some people hope to design a kind of RF ADC to replace the traditional front-end receiver network, sampling RF signal directly, which is not a myth. Although technological progress is a good thing and digital processing chips can complete computation and storage tasks faster and with lower power consumption, high-performance analog circuits design encounters great challenges that the performance of analog circuits are improved at the expense of power consumption and area, which restricts the applications. Nowadays ADCs can fulfill the conversion work with the help of powerful digital calibration, which looks like the coming trend.This paper focuses on the design and optimization of the first and second stages of Pipelined ADC with theory analysis and simulation verification, realizing a 16 bit 100MSPS high-speed high-resolution Pipelined ADC. It also tries to realize two-channel time-interleaved pipelined ADC without SHA. Whole pages discussed from four aspects as following:(1) System architecture. Using low power consumption SHA-less structure, it saves power consumption and contributes less noise compared with traditional sample-and-hold structure. The paper also gives resolutions to problems caused by new structure. Focusing on noise and power consumption, this paper first analyzes the main error sources by modules and deduces the minimum performance of basic circuits. An optimization analysis of noise and power consumption is referred at last.(2) Analog circuits. Design high-performance bootstrapped switch, operational amplifier and dynamic comparator. And a low jitter clock driver with 50% duty cycle corrector is proposed innovatively here. The opamp uses two-stage miller compensation structure with gain-boosting. Do small improvement to comparator to have faster regeneration time. Low jitter clock driver, in order to meet the need of high-speed application, try to optimize its jitter. The full-digital duty cycle corrector is added afterwards to improve time margin and guarantee ADC’s performance and reliability, which has short settling time.(3) Digital calibration. Use Matlab modeling and simulation to realize typical dithering calibration of the gain error and capacitance mismatch of the first pipelined stage through analysis and error model establishing.(4) Try to use two channel time-interleaved technology to speed up, and do analysis to the errors of two channel situation without SHA.The final simulation shows that single channel pipelined ADC can complete 100 MSPS 16bit conversion work and the results are good that SNDR is 76.8d B and SFDR is 100 d B at low input frequency. SNDR is75.7d B and SFDR is 97 d B at high input frequency. Two- channel pipelined ADC can realize 16 bit 200MSPS. SNDR is 76.7d B and SFDR is 100 d B at low input frequency. SNDR is 75.5d B and SFDR is 88 d B at high input frequency.