Design Of A 2.5Gb/s All-digital CDR And A Wide-Range Digital Control Oscillator

With the development of Internet, the demand of mass data transmission, the procession of High-Definition image and the application of network and communication, the demand for high bandwidth are becoming more and more serious. So, the serial data communication system has been a hotspot in the research area. While the clock and data recovery circuit plays an important role in the whole high-speed serial system and is the main bottleneck of the system.This paper presents an all-digital clock and data recovery; it is implemented in 0.18μm CMOS technology, and can recovery a pseudorandom bit sequence whose data rate can reach 2.5Gbps. This circuit is composed of full custom design modules and semi-custom design modules. The module phase detector, the frequency detector, the digital control oscillator, the detector circuit is designed in full custom design method, while the digital loop filter is designed in semi-custom design method. The frequency detector is composed of a probabilistic circuit to improve the accuracy of the frequency detection. The digital control oscillator is design by four stage differential ring circuit to get a better linearity. While for the digital loop filter, use a fast locking algorithm block to accelerate the preliminary locking process. After initial locked, to further reduce the jitter of the output of the clock, a jitter compression filter is added in this paper. Finally the layout is completed and the chip is taped out. It occupies an area of 0.26mm2, the post-layout simulation results show that the jitter of the output clock is less than 30ps, the power dissipation is less than 12mWwith a 1.8V power supply.This paper also presents the design of the digital control oscillator with the process of 0.13μm BiCMOS. Firstly the basic principle and structure of the digital control oscillator is introduced, and then the BiCMOS N type inverter is selected as the delay cell of the oscillator according to the process, and then the whole structure of the oscillator is determined. Lastly, the layout of the circuit is completed. And the post-layout simulation results show that the output frequency range of the oscillator is from 1.5GHz to 4.5GHz as well as the jitter of the output clock is less than5ps@4.5 GHz, and the vibration time is less than 10ns meeting the design requirements.Today, as the demand of the bandwidth in communication system is becoming more and more serious, the proposed all-digital clock and data recovery circuit is of great value in the communication systems, and the digital control oscillator has its value in the all-digital clock and data recovery circuit as well as the all-digital phase-locked loop.