Implementation Of Clock Recovery Algorithms In Real-time Digital Coherent Optical Communication System Based On FPGA

With the development and progress of society,the requirement of data transmission rate in real-time digital coherent optical communication system is getting higher and higher.In previous low-rate real-time digital coherent optical communication systems,because of the low data transmission rate,the parallelism of the digital signal processing(DSP)algoritlhm at the receiver side is low,it is easy to implement in field programmable gate array(FPGA),however,with the increase of data rate,it is necessary to implement higher parallel DSP algorithm in limited resource FPGA.In this paper,we focus on the parallelization of the clock recovery algorithm in the DSP algorithm.By improving the traditional parallel clock recovery algorithm,an improved parallel clock recovery algorithm with low complexity and less resource consumption is obtained.The specific research contents of this paper are divided into the following two parts:Firstly,the pseudo-code of parallel clock recovery algorithm based on MATLAB is completed,and the traditional parallel clock recovery algorithm is improved,by using sharing numerical control oscillator(SNCO)instead of independent numerical control oscillator(INCO),the algorithm resource is saved more than 16%under the same performance.The proposed algorithm is tested offline on the QPSK and 160AM experimental platforms of 2.5Gbaud.The performance of floating-point QPSK/16QAM traditional parallel clock recovery algorithms,fixed-point QPSK/16QAM traditional parallel clock recovery algorithms,floating-point QPSK/16QAM improved parallel clock recovery algorithms,fixed-point QPSK/16QAM improved parallel clock recovery algorithms are compared and analyzed.Secondly,the Verilog code of the QPSK parallel clock recovery algorithm based on Quartus ? is completed.The algorithm is verified by off-line experiments on the 2.5Gbaud QPSK off-line experimental platform based on FPGA,and on-line experimental verification based on FPGA of the above algorithm is carried out on the experimental platform of 2.5Gbaud QPSK real-time digital coherent optical communication.Based on the real-time parallel clock recovery algorithm implemented in this paper,the real-time clock recovery of 2.5Gbaud QPSK signal is realized.