.10 Gb / S Cmos Clock Recovery Circuit

In the recent twenty years, the great demand of telephone, fax, television and data led to the rapid development of optical communication. Optical communication and its technology achieved great progress. The foundation of American SONET and SDH accelerated the research and application of optical communication system. Nowadays, STM-16 (2.5Gb/s) has begun to construct extensively, and STM-64 (10Gb/s) has started to apply, and higher speed system is studying.Clock recovery circuit (CRC) is the key component in the optical transmission systems as well as in the field of digital transmission. As the standard of optical transmission Synchronous Digital Hierarchy (SDH) upgrades to STM-64 (10Gb/s) in recent years, the speed of IC chips must be promoted accordingly, but CRC is the main bottle-neck. Chips must also be highly integrated to fulfill the demand of high-reliability and low-cost. Therefore, CRC must be fully monolithic integration.This paper introduces a clock recovery circuit used for STM-64 (10 GHz) of SDH System which is realized in a standard 0.18 um CMOS technology. Above all, this paper introduced the basic conception of optical transmission systems and the architectures and fundamentals of CRC that is currently the most widely used in the optical transmission systems, and presented a new type of monolithic PLL called Injection-synchronized PLL. Then, we discussed noise in the circuits. Last, the circuit simulation, layout design and test results are presented.It is the principle of the Injection-synchronized PLL that The Synchronized Oscillator assists locking the PLL basing on the simple PLL. For the simple PLL, the noise is contrary .to the locking range, namely, the locking range is pretty small when the noise meets the need of the sysytem. Through the Injection-synchronized PLL, we can solve the problem above and make the loop more stable.The test results indicate that the CRC chip works on 10GHz and can aplly to STM-64 of SDH System.