Design Of Low Jitter Phase-locked Loops With Wide Frequency Range

Along with the ever-changing electronics propose high-speed requirements to IC design. The analog circuit design must follow with relationship of Mutual restraint that every performance parameters of Octagon laws. which makes for a certain performance parameters are very good, but it could be another performance parameters short board, so design analog circuit that applies to different condition and different environments simultaneously will proposed a great challenge.As a typical representative of the phase-locked loop, analog circuit design to achieve its low jitter is relatively easy when its input and output at a fixed frequency, but when the input or the output frequency changes, is bound to make some fixed loop parameters as a change the amount, this PLL system is a dynamic system witch to jitter performance of different frequency output point have not a good convergence, So wide range of input and output frequency low-jitter phase-locked loop design is a difficult.This paper studied the process under 40 nm CMOS low jitter to achieve a wide range of input and output frequency locked loop,through comprehensive research of system level, behavioral level, circuit-level and layout-level, three main factors of affect phase-locked loop output jitter: power supply noise, VCO control voltage fluctuations and jitter in the output frequency range of inconsistency.In order to achieve the jitter in the output frequency range of consistency, the paper improved adaptive bandwidth of a conventional PLL architecture,by the theoretical derivation, Verified its adaptation of bandwidth and damping factor with the reference frequency.To suppress voltage fluctuations of Vc, the paper analysis phase frequency detector and charge pump non-ideal factors of PLL from the behavioral level, and to develop a different solution based on different factors. Verification results show PLL in the locked state, this paper is designed so that the voltage controlled oscillator control signal from the peak from 2.1mV down to 0.13 mV, an order of magnitude decrease.In order to suppress the influence of noise on phase-locked loop output jitter, this article from the external phase-locked loop low dropout regulator designed to achieve weak noise power supply; then VCO modules were designed high power supply rejection ratio. The results show that the verification of this design strategy that 10% of the power supply noise are attenuated less than 0.5 %.Finally, to achieve a wide range of input and output frequency low-jitter phase locked loop under a 40 nm process, and design layout and test chips. Through the circuit and layout simulation results and the literature comparing PLL simulation results, this paper designed a very low jitter PLL, 10000 cycle cycle cycle peak to peak jitter less than 1%, RMS jitter is only 1.2 ‰, over the literature the same type of PLL. The PLL jitter and better consistency, a wide range of input and output frequency high-performance PLL requirements.