Design Of Low-power 50Mbps Clock And Data Recovery Circuit

Serial Link technology is the main method of the modern information transmission. In order to save the transfer cost and reduce the noise caused by sharing the clock, there is only data line. As the core Circuit, Clock data recovery circuit extracts clock information from the input data, and using the clock signal sampling the data to eliminate jitter which introduced by data transmission between sender and receiver. At present, the single chip Ethernet physical layer transceiver, whose low transmission rate and flexible power management architecture, lead to clock data recovery of low speed and low power consumption become the main demands.This paper focuses on the design of 50 Mbps clock data recovery circuit in SMIC 180 nm CMOS technology, which depend on PLL_based and with external reference clock, and in order to improve the stability, choosing the third order loop.In order to achieve low power consumption, voltage controlled oscillator(VCO) designed with one terminal five ring structure, and filter capacitor capacitance used the MOS tube to save the map area. Using verilog-A, combining XOR and shift register to realize the input random NRZ sequence. At last, CDR circuits locked in 74.6us,and the recovered data can follow the input correctly and Sample in the middle of the input data. The ripple on control line is 1.54 m V, and the peak jitter of recovered clock and data are 228.85 ps and 249.39 ps.considering the effects of substrate noise advance, when drawing the layout of CDR. Through all aspects of the measure to make up the deficiency of circuit design, the main method are improving match sexual, physical distance isolation and protection ring, etc.The clock peak jitter of postsim simulation is about 44 ps, which is obviously better than the imitation.At the same time, With the development of chip integration, substrate noise has become a problem of mixed signal circuit design. Digital circuit generate noise and inject it to the substrate, and damage sensitive analog circuit performance even system reduce reliability through the substrate.To analysis the influence of substrate noise specifically, through IC influence and substrate noise coupling principle, substrate model, N_well model and the power/ground model are applied to the CDR circuit. Through the simulation, substrate noise affects the output frequency of the VCO, extending the time of system lock, increasing the peak jitter of recovered clock damaging the loop stability. In order tosuppress substrate noise effectively, guard-ring was added, and the loop lock time reduced from 80.82 us noise to 74.3us, recovered clock jitter and jitter significantly reduced.