Research And Design Of All-digital PLL With High Frequency And Low Jitter Performance

PLL is a key component in many applications such as frequency synthesizer and the synchronization of communication. It is always a research difficulties and hotspot to design a low bandwidth and high performance PLL in the SOC applications.This article describes an all-digital PLL which utilizes a fractional-N PLL as its DCO, which overcomes the disadvantages such as sensitivity to noise, charge leakage, poor jitter performance and high cost that are encountered in traditional analog PLLs, and the low output clock frequency and poor jitter performance encountered in traditional all digital PLLs as well. As the fractional-N PLL is a high bandwidth design and with a very fine frequency resolution, furthermore it uses a crystal as the reference clock, so the all digital PLL introduced in this article can achieve very good jitter performance. Its output clock frequency can be very high due to the high frequency capacity of the VCO in the fractional-N PLL.The all-digital PLL has been implemented in UMC 0.13um process. The layout area is about 0.2mm~2. In the cadence mixed-signal simulation environment, the whole all-digital PLL simulation time is less than 1 hour. The digital part circuits are described by synthesizable RTL code. Thus the whole design period can be shortened.This design has been taped-out and tested. The test results show that the output clock RMS jitter is about 32.36ps.