Research And Design Of A Resolution-reconfigurable High Speed SAR ADC

Ultra-wideband medium-to-high resolution analog-to-digital converter, acting as data converter in the RF front-end, plays a crucial role in the field of wireless communications. As the process dismension keeps scaling down and the power supply keeps decreasing, the short-channel effect of devices becomes more significant and the design of high-performance analog circuit suffers from greater difficulties. The pipeline ADC, which was considered to be the best solution, now subjectes to the highperformance op-amp. Successive-approximation-register(SAR) ADC, with the advantages of simple-structure, low-power, area-efficient and digitally-dominant, has developed rapidly in recent years and now serves as the most optimal single channel solution for time-interleaved ADC applied in the field of wireless communications.The paper focuses on the research of high-speed medium-to-high resolution SAR ADC, including the technique details used to decrease the loop delay thus increasing the speed. A 10-12 bits 100 MS/s single channel resolution reconfigurable SAR ADC based on 55 nm 1P8M CMOS process is implemented. To achieve high performance, several techniques are utilized in this paper. To ensure the stability of system, the SAR ADC is designed with static logic, while dynamic logic suffers from the leakage and crosstalk, etc. To improve the conversion speed, the SAR ADC adopts the new SAR logic and DAC with low capacitance aiming at optimizing the digital delay and DAC settling time. A latch-type SAR unit is employed in the new SAR logic, which can improve the shortcomings of traditional high-latency trigger. A non-binary redundant DAC is introduced, which can reduce settling requirement and increase dynamic offset tolerance of each bit decision. To achieve high accuracy of system, the SAR ADC is designed to support two different switching method, enabling the digital calibration algorithm specified for time interleaved ADC. To improve the flexibility of system, the SAR ADC allows resolution-reconfigurable to deal with different requirements and applications, thus avoiding precision waste. To improve the system applicability, the SAR ADC utilizing self-adaptive circuit to control the loop delay, which can track the process, voltage and temperature variation in real-time and adjust itself accordingly. To control the chip cost, the SAR ADC design flow including layout design, post-simulation and circuit optimization is repeated for several time, striving to minimize the chip area while optimal performance is maintained.The post-simulation results show that the SAR ADC sampling a Nyquist frequency sine wave at 100 MS/s achieves a SFDR of 74.9 dB, a SNDR of 65.7 dB and an ENOB of 10.6 bits. The chip core occupies an area of 50×250 μm2 and consumes 15.5 mW with 1.2 V power supply, resulting in a FoM of 98.5 fJ/conv-step.