Research And Design Of High Speed Successive Approximation Analog-to-Digital Converter Based On CMOS Nanometer Prosess

The development of Internet of things needs to connect people's life with the Internet through intelligent perception and recognition technology so as to realize communication 3between objects and objects and people.Intelligent perception and recognition requires different kinds of sensors to realize wireless communication,as well as communication interconnection technology and RFID tags.The analog-to-digital Converter(ADC)is indispensable in this process.With the development of progress and technology,The advantages of SAR ADC in performance,area and power consumption are gradually highlighted with low power supply,and has been widely studied and applied.In this paper,by study high speed SAR ADC,the architecture characteristics of various high speed SAR ADC and the key factors that limit the speed of SAR ADC are analyzed.By using 40 nm CMOS process,this paper implements a 10 bit 160MS/s SAR ADC.By analyzing the non-ideal factors of MOSFET,a sampling circuit is designed with a CMOS switch.It effectively reduces the effect of channel charge injection and clock feed effect on sampling accuracy.Based on the non-binary DAC weights,the weight and redundancy of each capacitor are allocated reasonably,so that the establishment time is reduced.The DAC capacitance is splited,so that each time the voltage is set in the center of the redundant interval.No matter the set voltage of the DAC become higher or lower,it always can be compensated by the redundancy.In this paper,two comparators take turns to compare the voltage of DAC.In this way,SAR ADC can works at a high speed,and comparators have enough time to reset themselves.The comparator also have offset voltage calibration circuit,in case that a large offset voltage will affect the performance of SAR ADC.This has been simulated by using MATLAB.Asynchronous SAR logic circuit control the switches of DAC before SAR logic storages the results of comparators.So the delay time of storage will not influence the speed of SAR ADC.The simulation results of SAR ADC shows that the ADC achieves a SFDR of 71.26 d B,a SNDR of 61.57 d B,and an ENOB of 9.93 bit when it samples a Nyquist frequency sine wave at 160MS/s.The chip core occupies an area of 0.0158 mm2 and consumes 21.4 m W with 1.2 V power supply,resulting in a Fo M of 137 f J/conv-step.