Research And Implementation Of High Speed Low Power Successive-approximation Analog-to-digital Converter

One bottleneck of the 4G telecommunication technology is the multi-band multi-mode requirement for the RF receiver. In conventional solutions, multiple signal channels are independently designed for each band and mode. However, the interferences among different channels are very serious and the area and power are inefficient. Software-defined radio(SDR) technology provides another way to think about it, which utilizes an ultra-wideband analog-to-digital converter(UWB ADC) to quantize all the signals in the RF domain, and the demodulation of all the bands and modes is processed in the digital domain. SDR greatly lowers the difficulty in designing RF receiver, and needs no distinction of different bands, which is a very flexible solution. The UWB ADC usually adopts time-interleaved architecture, which parallelizes multiple low-speed single-channel ADCs to realize high-speed sampling. Nowadays, one emerging single-channel topology is the successive-approximation-register(SAR) ADC.SAR ADC is a common ADC prototype, possessing the merits of low-power, area-efficient, digitally-dominant,low conversion latency,etc,which is usually suitable for the low power applications of the low-to-medium speed and medium-to-high resolution. Nevertheless,due to the development of CMOS process technology and the innovation of asynchronous timing control,high-speed SAR ADCs have been thriving rapidly. For example,the typical sampling rate has been comparable to flash and pipelined ADC’s for the same resolution,while SAR ADC still outstands in its low-power. Therefore, it is currently enjoying the worldwide attraction in the high-speed applications. The dissertation emphasizes the research and implementation of a high-speed low-power SAR ADC, with the aim of satisfying the single-channel specification of a UWB ADC.The main work of this dissertation includes:First, a low power 10-bit 160MS/s SAR ADC is designed and implemented with several new high-speed techniques in 65 nm TSMC CMOS 1P6 M process. The measurement demonstrates that the SFDR is 65 dB and SNDR is 52.9 dB when a 30.1 MHz input signal is sampled at 160 MHz clock. The DNL is-0.47/+1.66 LSB and INL is-1.06/+1.18 LSB。The power is 9.5mW and the chip area is 250×200μm2. To achieve the sampling speed of 160MS/s,a number of systematic solutions are employed,such as asynchronous timing control, a top-plate sampling, a segmented DAC, low-power design, high-speed signal-integrity design and so on. Besides, there are a number of orginal ideas to optimize the delays in one bit-cycle, achieving a bit-cycle of less than 400 ps. For example, a new full-swing pre-charge bootstrapped switch as the sample-and-hold circuit is proposed which speeds up settling and effectively reduces the bootstrap capacitor. A partial “set-and-down” DAC switching algorithm is presented which switches the DAC fast and decreases the common-mode variation, alleviated the dynamic DC offset issue of the comaprator. A high-speed low-noise fully dynamic comparator adopts self-timed clock control to meet the conversion frequency of greater than 2GHz. In addition, the new SAR logic uses a “window-opening” method to replace the conventional shift-register-based logic, making the comparator results bypassing all the unnecessary DFFs and outputs the results directly to DAC, minimizing the delay, area and power.Second, the signal integrity is critical to high-speed circuit. For on-chip design, this work rationally seperates and shields the digital, analog, and buffer blocks to restrain the interferences from each other’s substrate. Decoupled capacitances are widely used to improve the power noise and maintain sufficient accuracy. The seperation of power domains fundamentally eliminates the crosstalk among analog and digital circuits. High-speed low-noise CMOS buffer effectively reduces the short-circuit current and improves the jitter of the output signal, power and ground. For PCB design, this work makes the differential signal routing, the combination of large and small sized decoupling capacitors, “least grounding loop” for digital outputs, and so on to maintain the expected accuracy.Third, a “top-down” mixed signal design flow is conducted. In the beginning, the Matlab behavioral simulation is done to determine the critical parameters. Then the transistor level simulation is carried out by Cadence Spectre to optimize the circuit design and reach the specifications. After that, a layout design through DRC, LVS and LPE to testify the post-layout performance is made. Moreover, the GDSII file is distributed to the foundry to manufacture the chip. Finally the PCB testbench is designed to measure and analyze the results.