The Influence Of The Bit-line Leakage Current On The Operation Of High Performance SRAM And Its Corresponding Elimination Techniques

With the ever increasing expansion of the applications in PC, network and mobile communications where to fast access and transfer data is needed, the demand for high-performance SRAM is increased significantly. But due to the progress of the semiconductor process, the leakage current of the transistor also shows up an ever increasing trend. This trend of the leakage current may lead to many problems and challenges for the SRAM design and one of the biggest challenges is that the ever increased leakage in the bitline may cause the performance of the SRAM to be postponed or even malfunctioning. As for this issue, the thesis explores the effects caused by the ever increased leakage current upon the high performance SRAM design and various techniques and schemes are also proposed to tackle the problems caused by the leakage current. The main researches are as follows:(1) A classical leakage current compensation circuit has been analyzed again in this thesis and by establishing a proper circuit model, it draws the conclusion that this kind of leakage current compensation mechanism may cause the performance of the SRAM to be degraded in some circumstances;(2) Based on the conclusion deduced from (1), two new leakage current compensation circuits have been proposed in this thesis. These two circuits cancel the phase of pre-determined then compensating the leakage current but to detect the slew rate of the two bitlines directly and generate the positive feedback paths automatically according to the difference between the slew rates of the two bitlines. The new leakage current compensation mechanism makes the bitline with lower slew rate to be discharged even slower and the bitline with higher slew rate to be discharged even faster so that the negative effect caused by larger leakage can be mitigated significantly;(3) Combined with one of the leakage current compensation circuits proposed in (2), a current type SA is proposed in this thesis to improve the performance of SRAM further under the background of the existence of nonnegligible bitline leakage;(4) If the leakage current is increased even more with the technology progresses, particularly when the accumulated bitline leakage exceeds the working current in the worst case, the traditional techniques and methods all tend to be malfunctioning. As a result, some exploratory researches have been done in this thesis and a kind of technique called bitline self cutting-off has been proposed to try to tackle the issue under this new category.(5) Due to the existence of the performance upper bound of the bitline self cutting-off technique proposed in (4), another new technique called inverted amplification of the bit-line voltage is proposed in this thesis as well. This new technique combines the techniques of the hierarchical bitline, the bitline self cutting-off, the charge sharing and so on to further improve the performance of the SRAM under the background of the existence of nonnegligible bitline leakage or even larger leakage current.