Search And Design Of Low-Voltage CMOS Static Random Access Memory

With the development of the Internet of Things,microprocessors have a greater demand for low power.Static Random Access Memory(SRAM)usually used as cache in a microprocessor.Decreasing the supply voltage is an effective method for low power.Decreasing the supply voltage makes a large effect on SRAM's operation.The effects mainlly include the following:(1)the speed and the stablity of conventional bit cells decrease quickly.(2)the leakage current of conventional bit cells become larger in standby mode at low supply voltage,which wastes a lot power.(3)the delay varietion of timing pathes increase at low supply voltage and the replicate bitline may enable SA at a wrong time.To solve the problems,this paper has verified the current techniques and pointed out the disadvantages.Then this paper proposes some new kind of circuits.The work of this paper is summarized below.(1)Study the circuit of bit cell and the cell's accessorial techniques,and propose a Schemitt-trigger based 10T bit cell.The ability of writing and reading is increased——the margin of writing increases 150%and the reading current increases 32%.In standby mode,the cell's leakage current decreases 38.4%.(2)To develop the conventional decoder,16 extra PMOS which controlled by the decoder's first level have been added to cut off the voltage in standby mode.The proposed decoder's dymanic power decreases16.8%,and static power decreases 75%.(3)A programale replicate bitline technique has been proposed.This replicate bitline technique can adjust the number of discharging cell by external signal.The technique increases SRAM's speed and energy efficiency,and makes SRAM operate at a larger voltage range.(4)A bit line leakage current compensation circuit is proposed to reduce the influence of cell's leakage current on bit line discharging.This circuit can reduce the bit line discharge delay by more than 64.1%,greatly improving the performance of SRAM under subthreshold voltage conditions.(5)A high-impedance input type sense amplifier with substrate bias is proposed.The speed of the designed sense amplifier is increased by more than 5.3%,and the standard deviation of the offset voltage deviation is reduced by 36.4%.The low-voltage SRAM is designed in SMIC 55nm 1P8M CMOS technology.The SRAM's area is 194370um~2 and it can operate at a minimum voltage of 300mV.At this voltage,the SRAM's operational frequency can reach250kHz and the power is 84.72nW.