Robustness Research Of SRAM Timing Control Circuit At Nanoscale

With the rapid development of mobile communication technology,3D technology,GPS navigation technology and high-speed wireless network technology,the modern integrated circuit design has been pursued to pursue a higher level of technology.In the On-chip system,embedded memory and other memory chip design has become an important part of the chip design.The percentage of the chip memory area will reach 90%in 2017.With the On-chip memory area and process variation increases,and power supply voltage reduction are making on-chip memory design face enormous challenges.Because of its high speed and low power consumption,static random access memory(SRAM)is widely used in mobile phones,personal computers and other electronic products.As a result,the performance of SRAM will directly affect the performance of SOC chip.The process variation of the Transistor threshold voltage(Vth)has a great impact on SRAM stability and access time.In this paper,the influence of process,voltage and temperature(PVT)on the stability of SRAM is studied in detail,and a more effective improvement technique is proposed.The main contents are as follows:Firstly,the structures of SRAM including memory array,sense amplifier,decoder,read-write control circuit and so on are introduced.The working principle of the memory array structure and the sense amplifier is introduced.Then,the principle of SRAM read operation is analyzed.Next,two kinds of timing control techniques(inverter chain delay technique and traditional replica bit-line technique)are introduced,and the comparison of these two techniques are present.The conclusion is obtained that the replica bit-line technology is more advantageous.Then,the author introduces some improved design of SRAM timing control circuit at home and abroad in recent years,and emphatically introduces and analyzes three kinds of design schemes,which are digital replica bit-line technology,Multi-stage dual replica bit-line delay technique,Dual-column staggered bit-lines delay technique,and their structure and principle are analyzed in detail,and some theoretical deductions are made.Finally,they are compared to the traditional bit-line technology by Monte Carlo simulation.Finally,this paper presente two improved technologies,the first is a double-row replication bit line technology,the second is based on bootstrap circuit replication bit line technology.In the past design,the improvements of the replica bit-line technique are from the structure itself.However,the proposed design innovatively improves the performance from the periphery circuit.The simulation results show that the scheme has achieved a good improvement effect without significant increase in area overhead.