The Architecture And Circuit Design For65nm High-performance SRAM

The embedded SRAM is an important part of the SoC chips.and its performance determines the performance improvement Of the whole SoC systems.In recent years. thanks to the development of the IC design methodology.EDA tecllnology and IC manufacturing process.the speed,density and power of the embedded SRAM have been imlproved signincantly. but the processing speed improvement of the microprocessor is higher than the SRAMs’.To further improve the SRAM performance is still the urgent needs of high-performance SoCIn this dissertation.a16Kb high-performance SRAM design is realized on the basis oftlle national key projeet.the key techniques researching of the SRAM compiler for embedded CPU.For meeting the requirements that the CLK to Q delay(Tcq)is less than800ps at the condition of1.2supply voltage.typjcal process corber and room temperature.and the area is less than28826.512um2.this dissertation Optilllizes the SRAM at the aspects of arcllitecture design.high-performance decoder design. accurate timing ciruit design and area optimization.At first.this thesis analyzes the advantages and disadvantages of the existing SRAM architecture design methods in detail.on the basis of the analysis and the feattires of the16Kb SRAM will be tealized,the memory array diVided method is chosen to realize the16Kb SRAM.To choose the optimal array divided method.two divided methods are simulated and compared,and finally the better one.which has the higher performance is chosen；Second,considering that the accurate timing control circuit design can improve the SRAM Operational speed and lowet the power dissipation effectively.this dissertation discusses the accurate timing control circuit desjgn methods.The jnverter chain delay method was used in the early time,but this method had the problem that the inverter chain delay couldn’t follow the delay of the melnory cell discharging the bit-line,and this problem is more significant as the process goes into the deep—sub micrometer.To resolve the problem,capacitance ratio replica bit—line technique and current ratiO replica bit-line technique is proposed.These two replica techniques use the replica bit-line and replica memory cell to emulate the bit-line capacitance and memory cell reading current, so they can follow the memory bit-line discharging time accurately. The problem of the two replica technique is that they can only generate the accurate timing signals at the fixed supply voltage, when they work in a voltage range, the bit-line discharging time will increased as the supply voltage rises. This dissertation proposes a programmable replica bit-line technique to guarantee the SRAM can generate the accurate timing control signals at a voltage range. The simulation and testing results show that the proposed technique can improve the SRAM performance effectively; At last, the CMOS static logic circuit is chosen to realize the decoder of the16Kb SRAM. When setting the transistor dimension in the decoder circuit, the thesis uses the logic effort analytical method to determine the fan-out of the logic gates and acquire the optimal delay of the logic chains. Because of the interconnect delay is comparable to the logic gates delay in65nm process, and the interconnecting line from pre-decoder to second level decoder is long, this dissertation discusses the logic paths design method which contain the interconnect, and finally the method is used to realize the high-speed decoder circuit of the16Kb SRAM.The post-iayout simulation shows the data reading out delay is540ps at1.2V supply voltage, and the value meet the design requirements. The16Kb SRAM is fabricated by using the SMIC65nm process, and the test results demonstrates that it can operate in a voltage range from0.8V to1.4V, and the operational frequency range is from440MHz to1.62GHz. The SRAM operational frequency is1.22GHz at1.2V supply voltage and room temperature, and the area is22762.76u.m2, much less than the value28826.512um2which is required. To verify the effect of the programmable replica bit-line technique, the SRAM using the current ratio is realized and compared. the results elaborate the new technique can improve the highest operation frequency from4.3%to9.5%as the supply voltage increased from0.8V to1.4V.