Design Of High Speed Low Power Embeded SRAM

As one of the most basic block in System On Chip (SOC), Static Random AccessMemory (SRAM) is growing rapidly in both speed and capacity with the development ofCMOS technology. However, high capacity means much more power consumption, lowpower consumption and high capacity SRAM is a popular and difficult research area intoday’s IC design.Based on application requirement, this paper proposed a full custom design of8K×32b SRAM. Bottom-up method was applied in the basic circuits design of the SRAM.At the beginning, cell bits in recent literature were listed and the performances werecompared, a6T cell was designed for the proposed design. The SRAM array was dividedinto four blocks by using divided wordline technology to lower down the powerconsumption. At the same time, pre-decoding and block decoding methods were used tomaintain high decoding speed and save much decoding area. For further reducing thepower consumption, gate-clocking technology was introduced and pre-charging circuitswere carefully designed to shorten the waiting time. Finally, to control the open time ofsense amplifier precisely and reduce the variation of process and external factors influence,improved replica bitline structure was used to control the sensitive amplifier clock. Moreaccurate control of the differential bitline voltage discharge to about100mV would reduceunnecessary discharge in bitline.In this paper a256Kb SRAM was proposed by SMIC0.18m CMOS technology inCadence Virtuso, full custom design methodology was used and the whole SRAM circuitswere simulated under Nanosim tool. Compared with the SRAM produced by memorycomplier automatically, the proposed SRAM achieves0.5ns read access time faster thanprevious one, and the total power consumption is only one eight of the former, so thispaper involves SRAM is suitable for low power consumption and high-speed SOCapplications.The innovation works in this paper include: design a high-speed decode circuit usinglogical effort method; point out that the traditional replica bitline structure may existproblems, and through simulation results to prove the existence of the problems. Improving replica bitline structure was proposed based on traditional replica bitline; usethe divided wordline technology and divided block technology to divide the SRAM arrayinto4blocks, which not only reduces the wordline load capacitance, but also speeds upthe read access time; at the same time, only activates the selected blocks, which cangreatly reduce the total power consumption.