Design Of Current-mirror Compensation Circuit For Multi-row Read In In-SRAM Computing

In recent years,with the rapid development of artificial intelligence,application areas such as machine learning and edge computing have become more and more extensive.These applications often require low power,low cost,and fast data read operations.However,the traditional separation of computation and storage of the von Neumann structure is an important factor hindering the development of these applications.In order to overcome the computational limitations imposed by these traditional von Neumann structures,the concept of in-memory computing was proposed.This article introduces the current research status of in-memory computing in beginning,and analyzes the working principle of SRAM in detail.SRAM has the advantages of high speed,low power consumption,and good compatibility with digital circuits,so it is mainly used as the cache of the CPU.Since the in-memory computing was proposed,the SRAM memory module has been one of the key research objects.The key technology of the in-memory computing is the multi-line read technology.This article analyzes several existing SRAM array-based in-memory computing technologies,and Multi-row Read techniques.Multi-row Read technology is the key technology of in-memory computing.Its accuracy will directly affect the accuracy of inmemory computing.Different from ordinary read operations,in-memory computing's each read operation turns on multiple wordlines at the same time,and the data weight mapping is completed by controlling the length of time that each wordline is turned on.For data with larger weights,a longer wordline turn-on time will cause discharge non-linearity,which will affect the accuracy of in-memory computing.In order to solve the problem of non-linearity of bitline discharge in Multi-row Read operation,a current mirror compensation circuit is designed based on TSMC 65 nm process.This compensation circuit acts on the bitline BL / BLB.For the data with a larger weight,when the bitline discharges to a certain voltage,the PMOS controls the current mirror to turn on,and the bitline continues to discharge through the discharge path of the current mirror,thereby achieving the purpose of compensation.This paper also proposes a structure that uses the replica bitline technology to generate 8T,4T,2T,and 1T wordline pulses that required for Multi-row Read.In this article,we use INL(Integral Nonlinearity)as a measure of whether the discharge is linear.In addition,we also use Monte Carlo simulation method as a basis for another measure.By analyzing the data we can get that the non-linearity of the data after compensation has decreased by about 72%.In addition,we also compared the Monte Carlo data obtained from the wordline pulses generated by the inverter chain and the replica bitline before and after compensation.It can also be concluded that the non-linearity of the bitline discharge is significantly improved.