Based On The Blms Digital Calibration Technology Of Low Power Design Of Pipeline Adc

As the interface between the analog world and the digital world, Analog-to-Digital Converters (ADC) are widely used in wireless communication systems, bio-medical instruments and consumer electronics products. With the rapid development of the CMOS technology, the digital signal processing has made considerable progress. The emergence of digital calibration technique has resulted in ADC achieving lower power dissipation and higher resolution. Among several ADC architectures, the features that pipelined ADC can achieve a good combination with digital calibration techniques and tradeoff between speed and resolution have made it to become a research hotspot at home and abroad.This pipelined ADC is implemented with1.5bit/stage pipelined architecture which can tolerate the offset error of the comparators better. Simultaneity the scale down of the sampling capacitances can decrease the power dissipation of the whole chip. The front-end Sample and Hold (SHA) circuit used in traditional pipelined ADC is abolished, a new configuration is proposed to match time constant requirement between the Mulitplying Digital-to-Analog Converter (MDAC) and the Sub-ADC input singal paths. In order to cooperate with Blind Least-Mean-Square (BLMS) calibration, MDAC is implemented in non-flip-around structure. The bootstrapped sampling switch is used to allow lower on-resistance and better linearity. Two stage opamp is adopted to maximize the output swing, the lower openloop gain which is only33dB not only simplify the opamp design but also consumes lower power. The costant-gm bias with tempertature compensation circuit assures the stability of the transistors under various process voltage and temperature conditions.This pipelined ADC is fabricated in0.13μm1.2V1P8M CMOS process. The chip occupies an area of4.7mm X4.3mm, consuming480mW, the analog core area is11.6mm whose power dissipation is380mW. Simulation Results shows that it achieves a signal-to-noise ratio (SNDR) of35.6dB for a3.13MHz sinusoid input and35.5dB for a83.13MHz sinusoid input at200MHz sampling clock. After the BLMS digital calibration, the SNDR attains78.1dB and75.1dB which increased by45.5dB and42.5dB compared to the results before digital calibration, respectively.