Apply To Research And Design Of The Pipelined Adc Can Be Configured In Multi-mode Wireless Communication System

As the development of wireless communication techniques, designing flexible and reconfigurable wireless transceiver is the focus of current research. To accommodate several standards such as WCDMA, TD-SCDMA and GSM, the ADC as a part of wireless transceiver should be reconfigurable with resolution and speed to meet the performance requirements with the lowest power for each standard. Meanwhile, the new generation wireless transceiver always integrates both analog and digital circuits on the same chip as to save the overall cost. Power supply is reduced as the scaling of CMOS technology, which would reduce power consumed by digital circuits, but also reduce the signal dynamic range and limit ADC resolution. So low power supply design is also a challenge in SOC using deep-micrometer or even nanometer process.The pipeline architecture adopted in this thesis is easy to realize reconfigurable design for its good trade-off between resolution, speed, area and power. High energy efficiency is achieved at each mode by adjusting currents of key blocks. To enlarge signal swing range at low power supply, this ADC uses two stage cascoded compensated OTA topology. The specific research contributions of this work include,1) The front-end SHA is removed with a proposed SubADC sampling network, which matches sampling circuit of the first stage residue amplifier much better.2) Except the first stage, OTAs with dual inputs are shared between successive stages as to cancell the conventional isolating switches.3) A low power on-chip reference voltage buffer is used to provide high accurate differential reference voltages for ADC.This ADC is implemented in 0.13um 1-Poly 8-Metal CMOS technology, and the core area is 1.40mm2. Thorough tape-out and chip test, the chip achieves an ENOB of more than 10.5 bits at each mode, while the peak SFDR and peak SNDR are 90dB and 69.2dB respectively, and the average FOM is about 0.46pJ/conv-step. At 5MHz sinusoidal input and 30.1MHz sampling rate, DNL and INL are-0.30～0.21LSB and-0.57～1.15LSB respectively.The ADC has been adopted in the chip of multi-mode wireless communication resceiver.