Research And Design On 16 Bit SAR ADC Based On 55nm Process

With the continuous development of the science and the technology, many blocks achieved through analog ways are gradually converting to digital means. As a result, it must complete analog singnals to digital singnals conversion through the ADC. In addition, the battery-powered equipments, data acquisition systems, medical instruments and seismic data acquisition systems need make some accurate processing about the analog signals, so the demand for high-precision ADC become more widely. Compared to other types of ADC, 16 bit SAR ADC has a great advantage, that is, existing a good compromise between the power consumption, accuracy and design complexity, so it is applied in more and more areas. As a result, based on 55 nm CMOS technology, we designed a 16 bit SAR ADC with high-precision.Firstly, using the software of Matlab make a model of the proposed 16 bit SAR ADC system and verify the correctness of the structure through simulating. To improve system’s performance, this paper analyzes the impact of non-ideal factors existing in the SAR ADC, including the impact of the DAC capacitor array’s mismatch and the input offset voltage and the equivalent input noise impact of the preamplifier and latch etc. Then we import these non-ideal factors to the ideal SAR ADC system model and verify the tolerance of the system. And that can assist in determining the circuit-level design specifications of each module.Secondly, we design each module in SAR ADC individually in this paper,including bandgap reference module, a high-precision comparator module, DAC capacitor array, switching circuit module and digital control module. To achieve a SAR ADC with high precision, we use the three levels preamplifier and renewable latch as the comparator’s structure, use "Split ADC" calibration techniques for SAR ADC capacitance calibration. In order to improve the linearity of the sampling switch, bootstrapped gate voltage switching technology is applied to improve the sampling switch’s gate voltage.Finally, based on the CMOS technology of the 55 nm, we simulate the whole 16 bit SAR ADC. Simulation results show that the sampling frequency is 250 KHZ, ADC’s SNR is 91.8 dB, SFDR is 116.3 dB, ENOB is 14.96 bit, where SNR, SFDR, ENOB are represented by ADC signal to noise ratio, spurious-free dynamic range, and effective number of bits and other dynamic properties.