Design And Implementation Of High-Speed Sampling Data Storage Controller

With the rapid development of information science, military electronic warfare and information science and other areas such as anti-missile radar, wireless communications and image processing will inevitably have to transmit high-speed large-capacity data. Therefore, high-speed data acquisition and caching technology has become the vital link in digital signal processing field so we need to use large-capacity, high data transfer rate storage medium in the high-speed data acquisition system. With the development of semiconductor technology, DRAM products began to emerge and rapidly evolving, from the beginning of the single-rate SDRAM gradually developed into the latest generation of the fourth generation of double data rate SDRAM in the market.Because the accessing request to the processor can not be directly identified by DRAM, so memory controller is required to complete the processor control, access to the DRAM. Research on the memory controller has become one of the focuses in high-speed data storage, embedded systems, high-performance computing research areas.This thesis studied DDR3 SDRAM JEDEC standard JESD79-3E, designed PHY Only memory controller and memory controller based on the program was uesed for high-speed acquisition and storage system. First, this paper combines memory type, speed, bandwidth requirements and other indicators in high-speed acquisition storage system and analyzes the feasibility of the controller design. Secondly, DDR3 principle and key technologies are analyzed in detail that provides a theoretical support for the design of the controller. In the end, this paper presents a PHY Only memory controller design. The program is only a DDR3 controller design of the physical layer, through ISE14.7 development tools, Modelsim10.1c simulation tool and Verilog HDL design input module,it make logic design and software simulation for FPGA design module of physical layer and high-speed acquisition storage systems and analyzes the performance advantages of the present program designed controller. Finally, using the ML605 hardware platform and Chipscope logic analyzer make resource consumption evaluation, performance test, board-level verification for high-speed acquisition storage system and controller, and finally do data analysis and near real time waveform display on the PC successfully.Verification results show that data throughput, cache size and read write speed can meet the requirements of the subject index in FPGA-based DDR3 high-speed acquisition memory system design. Stable operation under conditions of prolonged uninterrupted power, there is no error generated.