The Controller Design And Verification Of High Speed And Large Capacity Memory

Nowadays, the development of processor technology changes with each passing day, and the requirements of high speed and large capacity memory are also more stringent. And in all kinds of random memory, especially the use of DDR3 memory is the most widely used. DDR3 memory has many advantages, such as high speed, large capacity, low cost, and so on. Because memory is unable to make a direct response to the processor's visit to the memory, and the operation of the logic is very complex, the requirements of the read and write timing is also particularly strict, so design a good memory controller will be a long time trying to focus on in the future of this filed. In addition, the overall performance of the FPGA also grew rapidly in recent years. The new generation of FPGA has been able to provide more logic, faster computing speed and more abundant memory interface solutions. Therefore, the use of FPGA to support the design of memory controller is more and more developed by the researchers.In this paper, we choose the high speed and large capacity DDR3 memory as the research object. Based on the development of the high speed and large capacity memory, the characteristics of DDR3 memory chip and the use principle of DDR3 storage chip are analyzed in detail. Finally, a DDR3 controller based on Stratix IV Altera series FPGA is designed, which is integrated with the new UniPHY physical interface. After building the corresponding test platform, we complete the simulation test and the FPGA verification of the controller through the relevant software. As expected, the test results verify the validity of the controller design. The specific work is as follows:(1) Starting from the internal structure and working mechanism of DDR3 memory, the read and write control sequence are analyzed in detail.(2) The overall architecture of the DDR3 controller is systematically planned. The function, design idea and realization method of each subsystem are described in detail.(3) A detailed research of the internal structure of the new UniPHY IP core is carried out, and the design of the UniPHY physical interface is accomplished.(4) The software and hardware test platform is built. The data read and write function of the DDR3 controller is tested and verified by Modelsim and Quartus ? 12.1 software. The practical application value and the stability of the controller are guaranteed.