The Research And Implementation Of DLL In PHY Of DDR3 SDRAM Controller

Delay-Locked Loop (DLL) has been widely used in various timing systems because of its features of fast lock time and no sensitive to jitter . With the development of DDR3 SDRAM memory technology, the skew and jitter of system clock in memory controller has become more strictly, as a result, DLL plays a more important role in the DDR3 SDRAM memory controller.Based on the research of the DDR3 SDRAM memory controller and DLL theory thoroughly, an DLL is designed and realized in 0.13μm CMOS technology by full custom design, which is applied to DDR3 SDRAM memory controller for 400MHz,533MHz, 666.5MHz, and 800MHz. The post-layout simulation indicates that the DLL works correctly, and all kinds of specifications meet requrements of DDR3 controller.The main content of this works includes as below.1. A 32-phase voltage controlled delay line is designed and implemented in 0.13 um CMOS with the full-custom designing method, which can works at frequency 400MHz, 533MHz, 666.5MHz and 800MHz. The innovative difference voltage controlled delay cell is used to improve the capability of the voltage controlled delay line. The area of the DLL is 0.0089mm2, the average power dissipation is 27.3mW. The results of post layout simulation showed the DLL can meet the requirement of multiphase clock in DDR3 SDRAM memory controller.2. A innovative phase detector is proposed which combined the characteristic of conventional phase detector and binary phase detector. It solves the problem of dead zone in Charge Pump's switch transition and also has the perfect features of linear phase detector.3. Study the art of layout in physical design of mixed signal circuits, the techniques such as precise layouts matching and guard ring are adopted to design the layout of critical analog circuits. As a result, the noise from outside of critical analog circuits is decreased effectively.