Design Of DDR3 Controller Based On FPGA

Memory controller is an important part of the computer,memory performance directly affects the digital system performance.But memory cannot recognize the command sent from CPU,memory controller is in charge of processing these commands.Therefore,memory controller determines memory performance or even the overall digital system performance.DDR3 SDRAM as the current mainstream memory,it has low operating voltage,power consumption,high speed and large capacity,it has been widely used,largely satisfies the requirement of system storage.After researching on the study status in China and some other countries,the thesis analyses the working principle and technical characteristics of DDR3 SDRAM at first,to lay a theoretical foundation for the design of DDR3 controller,and then taking the external memory interface solution of Xilinx Corporation based on Virtex-6 series FPGA chip to design the overall structure of DDR3 controller IP core.With the top-down design methodology,the controller can be devided into logical control part and physical interface part on the whole,logical control part can be divided into the user.interface module,initialization module,Bank management module and some other modules,the physical interface part can be divided into clock reset management module,address command path module and some other modules,the thesis introduce these sub modules and accomplishes them with Verilog HDL.After completing the design of controller IP core,using Verilog HDL language to generate test platform,and then the controller IP core is simulated in ISE Design Suite 14.2 and ISim software,at last,this thesis presents the RTL simulation results of several key operations and analyses the simulation results.The memory controller IP core which is designed in the thesis has the following features:(1)It supports the overall series of Unbuffered ECC or Non-ECC memory modules,which capacity can up to 8Gigabytes.(2)It can recognize the module automatically and free to setting parameters.(3)It supports the peak speed of 800 MHz and the peak bandwith of 6.4GB/S.(4)The IP core can be used in embedded system,it has good flexibility and easy to transplant.