FPGA Design And Implementation Of High-speed CMOS Image Acquisition System Based On DDR3

In recent years,CMOS image sensor had the great improvement in the aspect of noise suppression and image quality.As the same time,image acquisition system performance requirements are also increasing.High-speed and stable image acquisition system became a key research direction.It has very important practical significance.This paper designed the FPGA program of CMOS high-speed image acquisition system based on DDR3.This program made the FPGA,DDR3 SDRAM and Camera Link effectively combined,it provided the better way and solution for the future research on high-speed CMOS image acquisition system.This paper first introduced the high-speed CMOS image acquisition system research significance and current situation of development at home and abroad;And then introduced the CMOS image sensor and DDR3 SDRAM work principle;Then the implementation of acquisition system is introduced in detail;Finally,we made the function simulation and verification on the test platform of the high-speed data acquisition system.In order to design a high-performance CMOS image acquisition system,this paper selected the GMAX0504 CMOS image sensor produced by the Gpixel as the image acquisition chip.The chip's resolution is 5144×3800 and its highest data transmission rate is 48Gb/s.Field-Programmable Gate Array is known for its high-speed parallel computing ability,the XC6SLX150 T FPGA of Xilinx Company is chosen as the control core of the CMOS image acquisition system.This system adopted two 2Gb DDR3 SDRAM chips of MT41J256M8-125 produced by Micron Corporation as cache units of image information.Camera Link is easy to connect,high-speed and stable,so this system transmitted the CMOS image information to the host computer by Camera Link interface for display.In the end,the verification results showed that the data transfer rate of CMOS high-speed data acquisition system is 12Gb/s,it realized high-speed data acquisition and transmission and completed the expected design objectives.