Design Of High-Speed ADC Performance Testing System Based On FPGA

With the continuous development of the global digital information industry,analog-digital conversion technology has been developed rapidly,leading to the extensive usage of good-performance analog-to-digital converter of new technology and structure.With the traction of 5G communication applications,the current high-speed ADC's conversion speed is rapidly increased from hundreds of megabytes per second to thousands of megabytes per second,and the data interface is also upgraded from the traditional parallel CMOS/LVDS to SERDES serial interface based on JESD204 B protocol.At present,new challenges to testing systems appear dure to the typical high-speed ADCs,such as ADI's AD9680(14bit/1000MSPS)and AD9625(12bit/2500MSPS).Traditional test system does not support the SERDES interface,and the slow data transmission speed and inadequate storage already cannot satisfy the actual testing requirements.Therefore,it has important practical significance to research the test system with high-speed data interface and large capacity storage space,whether for the design units and users of high-speed ADC.Firstly,a hardware scheme using high-speed FPGA Virtex-7 XC7VX485T-2FFG1761 C as the core of control unit based on the Xilinx VC707 hardware development platform is presented.Furthermore,the FPGA program and the host computer program are also provided to verify our high-speed ADC test system.The high-speed ADC test system can be compatible to a variety of high speed interface,and can be used to test various typical performance indicators.Compared with the existing test system,our system has the advantages listed below:1.Flexible interface.Our system supports three digital interface types: CMOS(clock frequency up to 300MHz),LVDS(clock frequency up to 650MHz)and JESD204B(clock frequency up to 12.5GHz);2.High data storage capacity and speed.By using a large capacity DDR3 SDRAM,the data throughput rate can be as high as 20Gbits/s,Take the 16 bits ADC as an example,our system can realize the continuous acquisition and storage of up to 512 megabytes sampling points;3.High data transfer rate.By using Gigabit Ethernet interface to upload data from the test board to the PC for further processing,and a data load of 77 Mbytes/s can be achieved.Secondly,a series of computer test programs are designed for the transmission of high-speed data,calculation of performance indicators and the graphical display.The test program has the advantages of both the object-oriented simplicity of MATLAB and the high-efficiency of C language in hardware control.The graphical user interface,index operation and results display are programmed using MATLAB,while the data transmission is realized using mixed programming of MATLAB and C language,and the high-speed ethernet data capture is achieved by extending MATLAB command through calling Win Pcap library by C language.Finally,the test system is used to test the two commercial ADC chips to evaluate their correctness,practicability and system reliability.The results show that the test system can fulfill the testing requirements of mainstream ADCs,such as AD9268 and AD9643,and has important significance in application and generalization.