The Design And Verification Of High-speed Storage Serface System Based On DDR3 Controller

DDR3 SDRAM as a new generation of memory, it provides higher operating efficiency and lower voltage relative to DDR2 SDRAM. The reason is that, DDR3 memory controller added some new designs as ZQ, SRT, 8bit prefetching, etc. ZQ is a termination resistor calibration function, this new pin can be used to calibrate internal termination resistors. SRT refers to the self-refresh temperature, it provides a programmable temperature controlled memory clock frequency function, which ensures that the memory particles will not be burned because of the high working memory clock frequency would leads increase of temperature. 8bit prefetching techniques can make the DRAM core frequency is only equivalent to 1/8 the data frequency, which is to ensure the efficiency of the external high-speed data bus when interacting. However, due to the internal DDR3 read and write operations with specific timing requirements in order to make it work properly. Therefore, in order to achieve successful completion of the complex read and write operations on bus it requires the use of a high-speed memory interface system for connecting external high-speed bus(e.g. PLB) and DDR3 memory controller.This paper designs a high-speed memory interface system to meet the needs of project based on the study of DDR3 JEDEC standard and PLB4 bus protocol. According to the requirements of the DDR3 memory controller user interface and PLB4 transmission mode, this paper designs the overall system architecture, which makes sure that not only all functions of this interface system but also the relationship between input and output can be normally good.This paper mainly complete RTL design of the entire interface system, and in the article details various modules in interface system with its internal composition and interface signals. Design challenge is how to complete the conversion between complex and diverse PLB4 bus transmission and the particular transport modes in DDR3 on the situation of cross clock domains. Besides that, there also has a further information on DDR3 memory controller state machine operating mode and jumps and PHY module’sinitialization and workflow.Based on the realization of RTL code design, I build a verification of the platform for the extraction, abstract verification items, and completed DDR3 controller-based interface system validation independently. The difficulty lies in the use of a specific language written verification bus functional items in bus functional model, and therefore would like to complete the platform needed to know how to build functional models and finish bus functional language learning, as well as verify the correctness of read and write data while DDR3 SDRAM read and write large amounts of data.