Design And Verification Of DDR3 Controller Ip Based On FPGA

Memory is an important part of computer system; Memory performance has a direct influence on the computer system. With respect to the magnetic storage and optical storage, semiconductor memory with its high speed, small size, high performance, large capacity and good compatibility has been widely used in many fields. At the same time, the problem of green environmental protection, low power consumption, but also to the memory of the development has brought new challenges.Due to the memory access request cannot be directly identify the processor, memory controller is responsible for the complete processor control operation of memory, and memory controller determines the maximum memory capacity of the computer system can use, number of memory, memory type and speed, memory, the data depth and width of grain and other important parameters. Therefore, the memory controller is one of the important factors to improve the overall performance impact memory performance and computer system.In this paper a detailed study of the technical specification document based DDR3 SDRAM memory by JEDEC on the command, through the analysis of the specific research process and working state of chip modules, control, summarizes the design scheme of a DDR3 SDRAM memory controller, And then using the top-down design method to complete the overall design of DDR3 controller.Complete the hardware design of the code, a detailed simulation using Modelsim simulation tools. After the completion of the controller circuit simulation in Cyclone IV series FPGA, and finally verifies the feasibility of the design, all the work is completed in this paper.