DDR3 SDRAM Controller Design Based On FPGA

With advances in semiconductor technology development and integrated circuit fabrication process, the memory has been unable to meet the demand for high-speed processor, high-bandwidth, high-capacity data access and storage of. As a new generation of DDR3 SDRAM DDR memory, relying on its efficient data transfer rates, cheap cost, good compatibility and high-capacity storage in a computer, consumer electronics and mobile communications and other fields has been widely used. Memory controller as a computer system, an important part, it is the bridge and link the data exchange between the microprocessor and memory, and its performance will directly determine the overall performance of the computer to play. So it has important practical significance and theoretical value for the study of the memory controller.A programmable logic device, FPGA with high integration, flexible structure and short development cycle and so on. The rapid development of FPGA accelerated its application in product design, functional simulation, etc., while, FPGA at ASIC prototyping and verification is also often stunning performance, most of the validation of this project were realized in FPGA devices.This paper analyzes the present situation of the development of the current storage controller, refer to the technical specifications JEDEC79-3A DDR3 and relevant information, then the existing related technologies careful study and comparison, its essence, abandoned its dross proposed DDR3 SDRAM controller FPGA-based designs, the main issue from the transport layer and physical layer ALTEMEMPHY two parts of its design. The physical layer uses a DDR3 memory controller interface provided by Altera Corporation. This paper focuses on the transport layer of the functional modules are designed in detail, and some of the key modules such as instruction decoding module, state machine module, asynchronous FIFO module, were RTL-level simulation.