Design And Implementation Of High-speed Storage System Based On FPGA And DDR3

The acquisition and storage system of the high-speed images is the basis of image digital processing,and the efficient cache controller is an indispensable part of the system.The DDR3 SDRAM has received more attention in the field of high-speed image acquisition and cache due to its excellent performance.However,the DDR3 SDRAM can work normally under the complicated read and write timings.At the same time,when high-speed image data is transmitted,directly reading and writing single frame data cause the frame interleaving.In order to ensure that the collected image data is stable and reliable,and the transmitted image data frame is complete,an efficient memory control system is proposed based on Micron's DDR3 SDRAM and FIFO+RAM structure.An incomplete ping-pong operation is presented to solve the frame interleaving problem.A multi-channel acquisition system is designed to improve the effective bandwidth utilization.The main work and innovations are:(1)A high-speed image data cache system integrating image acquisition,storage,and display is designed.FPGA is designed as the core of the system,and DDR3 SDRAM is the cache unit.The DDR3 SDRAM controller is based on MIG IP core to simplify the read and write sequence.The proposed incomplete ping-pong operation overcomes the disadvantages of traditional ping-pong operation.The complete image frames are obtained during high-speed image data transmission.A stable,reliable and easy-to-operate high-speed image data acquisition and cache system is realized.(2)For different FPGA chips,the format of the asynchronous FIFO IP core of VIVADO is different,which leads to the waste of bandwidth.Based on the VIVADO MIG IP core,an asynchronous FIFO with a read and write bit width ratio of 10:1 is implemented.A multi-channel read-write cache control module is constructed by combining the asynchronous FIFO and RAM.A8-channel parallel system is achieved to process the images with RGB888 data format and a resolution of 1920×1080.The bandwidth utilizationis improved.A test system is set up to test the effectiveness of the single-channel and multi-channel data acquisition systems.The test results are verified by the images on the display screen and the ILA logic analyzer of the VIVADO platform.Multiple test results show that the single-channel image acquisition and cache system realized by incomplete ping-pong operation are reliable,convenient to operate.There is no frame interleaving phenomenon.The multi-channel high-speed image data acquisition and cache system is verified on the Kintex-7 FPGA hardware platform.The calculated effective bandwidth utilization rate can reach 74.96% accroding th the ILA waveform.The result provide a reference for the multi-channel efficient data acquisition and cache system.