Design And Research Of A Delay Locked Loop For Clock Generator

Delay lock loop circuit, as a kind of high frequency clock generator, is an important research problem of recent CMOS circuit design. Compared to Phase lock loop, it has low jitter accumulation with the Voltage controlled delay line,so it has inimitable superiority in system stability,gain and bandwidth. For this reason, it is widely used. This thesis concerntrates on the DLL theory and a kind of DLL based on clock generator is proposed.In this paper, a new DLL structure is designed with a start controlled circuit in order to solve the problem that the traditional delay lock loop has the failure locking and harmonic locking problem during wide locking range operation. The loop filter capacitor is charged to the power supply when the power is on and the delay is minimum. During locking process, the power supply of the loop filter capacitor decreases continiously and the delay increases continiously until the phase difference between input single and output single equals to one cycle. A high-speed and low-power-consumption PFD using D flip-flop (DFF) structure with rising-edge detection is proposed. The CP is based on gain-boost structure, and some other auxiliary circuits are applied to better match the charge and discharge current. The Voltage controlled delay line adopts single-ended structure based on controllable current source which not only meets the request of system but also decrease the complexity of the whole circuit.The DLL designed in this paper is using XB0350.35μm CMOS process of X-FAB Corporation, and it is tested and simulated on Cadence platform with Spectre and SpectreRF simulator. Results show that the power supply is3.3V, the system output frequency range is from200MHz to400GHz, the locking time is less than60clock cycles and total power consumption is less than5mW.