Research And Design Of A DLL-Based Clock Generator In Time-Interleaved ADC

More recently, DLL-based clock generator gains wide popularity as a multiphase generator or for frequency multiplication in ADCs (Analog-to-Digital Converter), since there is no phase accumulation in DLL (Delay-Locked Loop). However, DLL-based clock generator inevitably suffers from static phase offset which is caused by imperfections in charge pump (CP) and phase detector (PD).The static phase offset can cause frequency shift on output of the clock generator, leading to sampling error in ADC. As the effective number of bits (ENOB) of an ADC is limited by both quantization step and sampling error, it is necessary to probe the effects of static phase offset on sampling error. Equations relating static phase offset with sampling error is derived in the thesis.A DLL-based clock generator that minimizes the static phase offset in PFD (Phase Frequency Detector) is designed for a 12-channel 6-bit 600-MS/s time-interleaved ADC. The DLL produces 12-phase signals and a multiplied clock with a multiplication factor of 6. A novel transecting PFD is introduced to compensate the static phase offset in PFD and CP in order to reduce output jitter of the clock generator.The DLL-based clock generator is fabricated in TSMC 65nm CMOS process and occupies an active area of 90μm×110μm. The clock generator shows a continuous lock range from 34MHz to 100MHz. Measurements on DLL phase noise, static phase offset and jitter performance are presented at 50MHz reference clock. The measured phase noise is -91dBc/Hz@1kHz and -109dBc/Hz@1MHz. The relative rms jitter is 2.97° and the static phase offset is 145.5ps.