Design Of Clock Generator Based On Delay-Locked Loop

With the development of communication technology and integrated circuits process, the speed of digital signal processing and transmission is becoming incredible. Besides, the slew rate between analog signals and digital signals is more and more rapidly. As a result, the requirement of clock signal quality is rigorous. It is necessary to design a high-performance clock generator. Clock generators can be widely used in interface circuits, ASIC, clock and data recoveries, microprocessors, etc.A low-power low-jitter DLL-based clock generator is presented in this paper based on the analysis and research on the principle of clock generators. The clock generator proposed in this paper consists of a DLL, a frequency multiplier and an antiharmonic-lock circuit. Compared with conventional DLL, a phase_error compensation blobk is added to the proposed DLL so that the clock generator can keep track of any potiential phase error introduced by unwanted environmental variations or reference frequency instability. In the frequency multiplier, the multiplication factors-×2,×4, 6, 12 are programmable. Moreover, the pulse-conbiner circuit is mainly composed of MOS transistors instead of logic gates, which decreases jitter and power consumption. The antiharmonic-lock circuit uses only two lock phases of multiphase clock, and it can detect whether the DLL is in the harmonic-lock state or not over a wide range.The proposed DLL-based clock generator is applyment in a SMIC 0.18-μm COMS technology. It can take input reference frequencies from 25MHz to 150MHz at power voltage 1.8V. Simulation results show that the DLL can be locked within 15 clock cycles and generates 24 uniformly-spaced phase-shifted signals. According to the programmed 2-bit signals, the frequency multiplier selects phase-shifted signals among 24 streams and provides a multiplied clock. The 50% duty cycle ratio can be achieved by any frequency multiplication factor-×2,×4,×6,×12 of the DLL-based clock generator, without any risk of harmonic locking.