Research And Implementation Of A DLL Based On Multiphase-Clock Generator

Delay-locked Loop(DLL), as a kind of high frequency clock generator, is one important research problem of recent CMOS circuit design. It has inimitable superiority and funetion in reducing the output signal jitter and reducing the locked time compared with the traditional Phase-locked Loop(PLL). This subject,which is from the I/O group of Design Services at SMIC, is going to design a DLL system used in DVI_RX based on SMIC0.13μm CMOS arts.In this paper, the basic theory of high frequency clock generator is described in detail firstly, including the theory, structure, characteristics and application of PLL, CPPLL, DLL. Then, the stability of Delayed-Locked Loop circuit is analyzed through the mathematical models. The method of phase jitter analysis and summarize the method of the noise and means to resolve are described. Finally, the paper introduces the different structures of DLL briefly and compares their advantages and disadvantages. Accomplish a DLL design based on SMIC0.13μm CMOS arts. It utilized a total process of DLL develpment from circuit design, pre-layout simulation, layout design, post-layout simulation and optimize till to the final tapeout. It achieved the purpose of lower jitter, faster locked time and the application requirements by using the new circuit and improving the original circuit.