Font Size: a A A

Design Of DLL Based Multiphase Clock Generator

Posted on:2011-04-26Degree:MasterType:Thesis
Country:ChinaCandidate:Z M ChenFull Text:PDF
GTID:2178360308963553Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Compared to Phase Locked Loop (PLL), Delay Locked loop has much better stability characteristic and low jitter accumlation, hence, it is widely used, This thesis concerntrates on the application that DLL is used as a high performance clock gernerator , A DLL based multiphase clock gernerator adopting CMOS process is proposed.Conventional DLL has the failure locking and harmonic lcoking problem during wide locking rang operation, therefore, the DLL operationg frequency range is limited, In order to overcome these problems, Firstly, the operation principal of conventional DLL is analysed, and the reason for the problems is presented, Then a new DLL structure is designed, which adds a start controlled circuit and novel phase detector into the conventional DLL, The loop filter capaciotr is charged to the power supply when the power is on, The new structure phase detector splits the DLL locking process into coarse tuning stage and fine tuning stage, the conventional DLL problems are fixed during the coarse tuning stage, what's more, the locking time is reduced, The new structure DLL is verified by the Verilog-A model, For the circuit desgin, the ciruit topology is optimized, a trade off between power consumption , area and circuit performance is considered, High performace charge pump is desgined, which reduces the mismatch between charge current and discharge current, thus, the static locking error is reudced, The Voltage controlled delay line adopts differential input and differential output structure, improving the DLL anti nosie capability.The DLL based mulitiphase clock gernerator can output 8 pahse clocks, the phase differernce between adjacent clocks is 45 degree, DLL uses the GSMC 0.13μm 1P7M CMOS standard process, power supply is 1.2V, and core area is 265μm×214μm. Simulate with the variations of corner, power supply 10% variation and temperature(-40°-125°), when the input frequency range is 300MHz-500MHz, the lcoking time is less than 3μs, staic phase error and jitter are all less than 10ps, the duty cycle error is less 5%, that's 2.25 degree, Total power consumption is less 3 mW.
Keywords/Search Tags:Delay locked loop, Clock generator, Charge pump, VCDL
PDF Full Text Request
Related items