Asic Implementation Of The DDS Based On Improved CORDIC Algorithm

Direct Digital Frequency Synthesizer systems are characterized by fast frequency phase amplitude switching, excellent frequency resolution, low phase noise, and transient-free frequency changes. DDS plays a key role in wide areas of digital electronics, such as in digital communications, electronic warfare and radar systems, test and measurement equipments, and medical equipments.With the feature size of process becomes smaller and the continual improvement of the chip’s integration level, the research of DDS focused on system’s low latency, ultra-high speed, and low power.Based on the project of 14 bit 2.5GHz DDS & IP core design, this paper analyzes the principle, structure, and error sources of the DDS system. In DDS system, the phase is obtained by frequency accumulation, and the phase information is transformed into sinusoidal amplitude value directly. This process is a nonlinear mapping, which is usually implemented by digital method. Amplitude signal is converted to the required frequency signal by the DAC and is filtered to smooth. It consists of three blocks: a phase accumulator, a phase-to-sinusoid amplitude converter and a digital-to-analog converter. Its error source includes phase truncation error, amplitude quantization error, nonideal DAC and phase to sineamplitude conversion error. This paper is focused on the algorithm of the phase to sine amplitude converter and how to realize it.Five kinds of phase to sine amplitude conversion are analyzed and compared, and CORDIC algorithm is choosed which is easy to use CMOS technology to achieve high accuracy. However, using the traditional CORDIC algorithm to realize the phase to amplitude converter, there are two shortcomings. First, it needs to determine the direction of each rotation. Second, the number of iterations is too big. In order to solve these two problems, trigonometric function approximation is used, the previous stages which cannot use approximation use small lookup table to realize, the stages which can use approximation are combined to reduce the number of rotations, an improved CORDIC algorithm is obtained. The new method eliminates the judgment the direction of each rotation, and the number of the rotation is reduced to1/3. On the 0.18μm CMOS process, a 14 bit 2.5GHz DDS chip is realized based on the improved CORDIC algorithm, and type-out, package, test.The DDS chip’s frequency change time is just 3.2ns, frequency control word is 32 bit, phase offset word is 16 bit, amplitude control word is 14 bit, and support frequency, phase, amplitude linear sweep operation. The test results show that, the work frequency of the designed DDS achieves 2.5GHz, and the control function of frequency, phase, and amplitude is proper, wide-band SFDR is 56 dBc at low out frequency and 41 at high out frequency(80% of the Nyquist frequency).