Design Of High Speed DDS Based On Improved CORDIC Algorithm

With the development of digital and microelectronics technology,signal sources based on Direct Digital Frequency Synthesis(DDS)have been widely used in many fields.Since the demand for signal generators in terms of frequency range,spectral purity and frequency resolution is increasing,improving the performance of signal generators while controlling the cost has become one of the research directions in this field.The lookup table scheme is the most common phase to amplitude conversion method in current DDS.This method pre-quantizes the amplitude of a sine wave of one cycle and stores it in memory,and then obtains the amplitude based on phase addressing.To increase the frequency resolution and spectral purity of the DDS source,the lookup table capacity needs to be increased,and the multiphase scheme is commonly used in high sampling rate DDS,which makes the lookup table capacity increase exponentially,so the dependence of the lookup table scheme on the memory will bring greater complexity and cost.Coordinate Rotation Digital Computer(CORDIC)is a logic operation to achieve the phase amplitude conversion,which is fast,high accuracy and no storage resource consumption,this method has obvious advantages in the high-speed multi-phase DDS source architecture.In this paper,a 1G sampling rate DDS signal generator is designed and completed based on the CORDIC algorithm,and the main work is as follows.(1)Start with the principle of DDS,MATLAB simulation is used to analyze the effect of phase and amplitude quantization bit widths on the SFDR of DDS output spurious-free dynamic range separately and simultaneously,and it is concluded that the SFDR of DDS source will be increased by 6dB for each bit increase of phase or amplitude quantization bit width.For a DDS with 24-bit phase bit width and 14-bit amplitude bit width,the SFDR is about 88dB,and the four-phase DDS lookup table requires 128MB of off-chip memory,which is obviously high in complexity and cost,and the direct calculation method has obvious advantages.(2)The improved CORDIC algorithm is introduced into the DDS design scheme of FPGA,and the algorithm is optimized by adding and subtracting configurable operation units,parallel addition trees and other structures,and a CORDIC core with phase and amplitude quantization bit widths of 24 and 14 bits respectively is implemented on FPGA.The test results show that the algorithm has a build time slack of 93ps and a hold time slack of 55ps under the clock constraint of 250MHz,and the computational error of the algorithm is only,which meets the requirements of DDS design.(3)Design the hardware circuit of DDS based on CORDIC algorithm.It includes FPGA circuit,external clock source,DAC and output signal conditioning circuit,etc.By standardizing the layout and wiring and reasonably designing the cascade structure,the high-speed analog-digital hybrid system is stable and reliable.The test results of CORDIC-based DDS source show that the SFDR is 86.77dB and harmonic distortion is better than-35dBc at a sampling rate of 1GSa/s and a maximum output frequency of 350MHz;the maximum harmonic distortion is-50dBc below 100MHz;and the phase noise is better than-110dBc/Hz at a frequency bias of 10kHz at multiple frequencies.Compared with commercial DDS signal sources,it saves a lot of storage resources and reduces design complexity and cost.