Research And Implementation Of DDFS And FFT Based On The Enhanced CORDIC

Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm, which uses a series of fixed angles backward and forward rotation in an iterative manner to approach the target angle, simply needs shift and addition operations, and it is feasible to be implemented by a pipelined method. CORDIC algorithm has been widely used in many aspects, such as multiplication, trigonometric function, extraction of root, FIR etc. This paper investigates the conventional CORDIC algorithm and proposes some enhanced structures, then presents the designs and implementations of Direct Digital Frequency Synthesizer (DDFS) and Fast Fourier Transform (FFT) coprocessor. Main contributions of this thesis are listed as follows.1. There are some limitations in Conventional CORDIC algorithm, for example scaling factor, limited convergence range and excessive number of iterative times. This paper proposes two enhanced structures, the first one named entirely covered K2 CORDIC architecture, without pre-processing and post-processing units, extends the convergence range of the rotation angle to the entire coordinate, while the performance is improved by two bits. The other called self-adaptive recoding CORDIC, which bases on the principle of Scaling Free (SF), eliminates the scaling factor and reduces the iterative numbers with no performance penalty.2. Researching and implementing DDFS based on CORDIC. The unit of Phase to Amplitude in conventional DDFS always uses Look-Up-Table (LUT), however the precision is restricted by area. In this paper, by using the enhanced self-adaptive recoding CORDIC instead of LUT, the trigonometric function values are generated in a realtime. The novel structure reduces the consumed hardware significantly, while the precision is up to 11 bits. The proposed architecture has been verified on Xilinx FPGA development platform, and the layout is achieved by the tools of Place & Route in Xilinx ISE.3. A CORDIC-based high-speed FFT coprocessor is designed and implemented in this paper. The Butterfly-Operation units in the conventional FFT are composed of imaginary multipliers and adders. The speed of FFT is constrainted by the complexity of multipliers. Moreover the twiddle factors take up many resources. We design a novel CORDIC-based multiplier, and propose a novel approach which generates twiddle factors in a realtime according to address. Furthermore, a conflict-free memory access schemeis is also proposed. Hence, the system speed is improved significantly. The FFT coprocessor has been simulated and verified, comparing with conventional 50MHz the proposed one can achieve 113MHz.