ASIC Design Of DDS

Direct Digital Synthesis(DDS) technology is the third frequency synthesis technology after the direct frequency synthesis and the indirect analog frequency synthesis. Because of its high frequency resolution,fast frequency switching time,good phase continuity,low phase noise and some other advantages compared to other frequency synthesis technologies, DDS technology is widely used in communication systems,remote sensing,power electronics and other fields.Direct digital frequency synthesizer primarily consists of phase accumulator, phase and amplitude converter, digital to analog converter and low-pass filter. The design of the traditional DDS is mainly based on look-up table to achieve, which put the output value corresponding to the phase store in ROM, and require the output waveform by addressing. Although the look-up table method is simple and easy to implement, its accuracy is limited by the ROM storage capacity, and high-precision output requires a large ROM storage capacity, so it must occupy a large chip area and power. In the paper, CORDIC algorithm unit is put to replace the look-up table structure to achieve DDS system. throungh the improvement of the CORDIC algorithm, a new CORDIC algorithm struture which consumes less resources is proposed and applicated in the design of DDS circuit..The paper first introduces the basic concepts of frequency synthesis, gives the advantages and disadvantages of three kinds of frequency synthesis technology, and illustrats the development of the DDS. Then the paper detailed analyze the structure and the basic principles of DDS and the spurious reasons, sum up the several compression algorithm of ROM, and take the deep research of the traditional CORDIC algorithm. Because the traditional CORDIC algorithm need to calculate the direction of rotation of each level iterration, the algorithm not only reduces the computational speed, but also would occuply more source of system. So the paper present an improved CORDIC algorithm, the algorithm can calculate part of the direction of rotation in advance. After Modelsim and Quartus soft simulation, the algorithm can improve system output accuracy, with a relavently small storage capacity, and significantly save the system resources. Finally the front-end design of DDS system with ASIC design flow is accomplished. After synthesising under SMIC 0.35um standard cell technology library, the synthesied circuit area is about 30000um2, power consumption is about 136mW.